The present disclosure relates to electronic systems and methods, and in particular, to latching circuits and methods.
A latch is a circuit that typically has two stable states and can be used to capture and store information. Latching information may be implemented in a variety of ways. One example latching circuit is a logic circuit that receives digital signals and is configured to have a bistable output, where the output resolves into one of two stable states. Example logic circuits that are commonly used as latches include inverters, SR latches, JK latches, and D latches (sometimes referred to as “Flip Flops”).
Comparator circuits sometimes use latch circuits to capture the result of a comparison operation. Performance of the comparator can become highly dependent on the performance of the latch circuit following a comparison circuit. For example, in high speed analog-to-digital converters (“ADCs”) (e.g. SAR, flash ADCs), the overall conversion time of the ADC may depend on the speed of the comparator, which is dependent on the ability of the latch to resolve to a final output. The latency of a latch, in turn, can depend on supply voltage variations. For example, at low supply voltages, the latency of a complementary latch increases due to the reduction of the bias current at low supply voltages, for example. Latches must also be stable over variations in the supply voltage during operation. Thus, as supply voltages decrease, there is a need to find faster circuits for performing the latching function that perform well over variations in the supply voltage.